Bio: Barbara P Aichinger is Vice President and co-founder of FuturePlus Systems. She holds both Bachelors (University of Akron) and Masters (University of Massachusetts at Lowell) degrees in Electrical Engineering. Barbara’s expertise is in computer bus architecture. She has over 30 years of experience in standards organizations involved in computer bus architecture. She is a member of the IEEE, a JEDEC Committee member (DDR Memory) and a VESA DisplayPort Task Group member. She is a frequent public speaker on topics of DDR Memory and DisplayPort. Her main area of interest is in test and validation with emphasis on finding problems prior to production. She was one of the early champions that notified the engineering community of the Row Hammer failures effecting DDR Memory. She blogs frequently on her companies web site and has many articles on LinkedIN. Barbara is married and has 3 children. In her spare time she plays tennis, snow skis and loves to boat on Lake Winnipesaukee in New Hampshire.
Bio: Kuljit is the Chief Architect of Intel’s Memory & IO Technologies group and an Intel fellow. Over the past couple of decades, he has overseen the design and specifications of many types of DRAM including DDR3, DDR4, DDR5, LPDDR4, LPDDR5, HBM3, and NVDIMM. His deep knowledge of DRAM architecture and memory sub-systems has made Kuljit influence DRAM standards across server, client, accelerator, and graphics market segments. Over his career, Kuljit has authored many patents, some of which put forward the earliest ideas on how to improve DRAM security going as far back as 2012.
University of Michigan
Bio: Daniel Genkin is an Assistant Professor at the Department of Electrical Engineering and Computer Science at the University of Michigan. Before joining Michigan, he was a Postdoctoral Fellow at the University of Pennsylvania and the University of Maryland. Daniel’s research interests are in hardware and system security, with particular focus on side channel attacks and defenses. More recently, Daniel has been part of the team performing the first analysis of speculative and transient execution, resulting in the discovery of Spectre, Meltdown, Foreshadow, and followups.
Taek Woon Kim
Bio: Taek Woon Kim is a staff engineer of DRAM product planning in Samsung Electronics, and his core interest is standardization of SDRAMs like DDR, HBM, and GDDR. Taek Kim is a chair of JEDEC’s DDRx sub-committee, JC-42.3, which is targetting to standardize DDR product families. He’s also a vice-chair of Joint Task Group for Data Integrity, which is seeking for the path to eliminate Rowhammer.
Bio: Onur Mutlu is a Professor of Computer Science at ETH Zürich. He is also a faculty member at Carnegie Mellon University, where he previously held the Strecker Early Career Professorship. His current broader research interests are in computer architecture, systems, hardware security, and bioinformatics. A variety of techniques he, along with his group and collaborators, has invented over the years have influenced industry and have been employed in commercial microprocessors and memory/storage systems. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. He started the Computer Architecture Group at Microsoft Research (2006-2009), and held various product and research positions at Intel Corporation, Advanced Micro Devices, VMware, and Google. He received the IEEE High Performance Computer Architecture Test of Time Award, the IEEE Computer Society Edward J. McCluskey Technical Achievement Award, ACM SIGARCH Maurice Wilkes Award, the inaugural IEEE Computer Society Young Computer Architect Award, the inaugural Intel Early Career Faculty Award, US National Science Foundation CAREER Award, Carnegie Mellon University Ladd Research Award, faculty partnership awards from various companies, and a healthy number of best paper or “Top Pick” paper recognitions at various computer systems, architecture, and security venues. He is an ACM Fellow “for contributions to computer architecture research, especially in memory systems”, IEEE Fellow for “contributions to computer architecture research and practice”, and an elected member of the Academy of Europe (Academia Europaea). His computer architecture and digital logic design course lectures and materials are freely available on YouTube, and his research group makes a wide variety of software and hardware artifacts freely available online. For more information, please see his webpage.