DRAM is the most prevalent memory technology used in laptops, mobile phones, workstations and servers. As such, its security is paramount, yet DRAM attacks remain as viable as ever despite many attempts to resolve its security problems: as an example, recent work has shown that modern DRAM remains vulnerable to Rowhammer, and in fact, newer chips are even more vulnerable than older ones. DRAM is also plagued by additional forms of attack including side-channel, Denial-of-Service (DoS) and cold-boot attacks.

DRAM security defenses are now at an impasse: the research community’s proposals do not take the practical constraints of DRAM devices into consideration while the industry is adopting obscure and ineffective remedies. There are huge ongoing efforts in industry to design safer and more reliable DRAM. Unfortunately, most of these efforts receive little input from the academic community. The goal of this workshop is to bridge these communities and to seek contributions from both academia and industry on the broad topic of DRAM security.

Tentative workshop program

DRAMSec will be a virtual event. We are making efforts to create a schedule that can accommodate most timezones. An option we are considering is to have each presentation occur twice to give attendees more flexibility to attend the presentation and the Q&A afterwards. Here’s a tentative schedule starting on May 21st:

Time CET Time PST Topic
20:00 - 20:10 11:00 - 11:10 (am) Welcome by chairs
20:10 - 21:50 11:10 - 11:50 (am) Paper presentations (incl. a break)
22:00 - 22:50 12:00 - 12:50 (pm) Keynote
23:00 - 00:00 01:00 - 02:00 (pm) Panel
00:10 - 01:50 02:10 - 03:50 (pm) Paper presentations repeat (incl. a break)

Call for papers

We are soliciting papers on attacks and defenses on current and future DRAM technologies. The program committee will favor papers that bring new insights, debunk previously held beliefs, re-visit assumptions, present new attacks and defenses, or put forward controversial points of view. We also consider position papers especially from industry that outline design and process challenges affecting DRAM security, new forms of secure DRAM, or describe state-of-the-art DRAM defenses.

Submissions must be original, unpublished work, and not under consideration at another conference or journal. The authors must use the DRAMSec hotcrp for submitting their papers. Papers must be formatted for US letter (not A4) size paper using the Microsoft Word or LaTeX templates provided on the IEEE website. The length of the submitted papers should be 5 pages at maximum, excluding references. Appendices count towards the page limit, while the main body of the paper should be self-contained. Paper submissions will go through a double-blind reviewing process by the DRAMSec program committee and should not include author names or affiliations. At least one author for each accepted paper is required to present the paper at the workshop.

We expect that at least some papers at DRAMSec would represent “work-in-progress” projects. Therefore, authors of published papers could choose to extend their work to full-length conference papers later.

Topics of interest

Dates

Workshop chairs

Program committee

Sponsors



Based on the Researcher theme